The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method of semiconductor device formation with a simplified process flow. Merely by way of example, the invention has been applied to the formation of SONOS-based non-volatile memory or flash technologies, but it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to remove a layer and form structures without damaging the active device.
As merely an example, etching processes are often used to remove or partially remove a layer to form structures therefrom. Etching is often performed by an etching tool, such as a dry etcher or wet etcher. The wet etcher often includes a vessel that has an etchant chemical to selectively remove one material from another material. The dry etcher often includes a plasma source and treatment chamber. The dry etcher often uses gases such as fluorine bearing species and chlorine bearing species to remove semiconductor materials such as silicon or metal such as aluminum. For example, dry and wet etchers may be used within the formation of SONOS-based non-volatile memory or flash memories. A conventional polysilicon gate etch process consists of a two-step etch process used to etch the polysilicon and ONO layers. The first step etches away polysilicon and stops at the top oxide layer of the ONO layer within both the cell and periphery regions. A second etch step etches the top oxide and silicon nitride of the ONO layer away and stops at the remaining oxide. The two-step poly gate etch process is used to ensure that both the periphery and cell devices can obtain the best gate etch profile without degrading device performance. However, a simplified poly gate etch process could be used, thus simplifying the process flow and providing improved process efficiency.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.